1. Field of the Invention
The present invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and on other programmable resistive materials, and methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the molten phase change material and allowing at least a portion of the phase change material to stabilize in the amorphous state. It is desirable to minimize the magnitude of the current needed to cause transition of phase change material.
The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the size of electrodes in contact with the phase change material element, so that higher current densities are achieved with small absolute current values through the phase change material.
However, attempts to reduce the size of the phase change material element and/or the electrodes can result in electrical and mechanical reliability issues of the cell because of failures associated with the small contact surface therebetween. These failures include the formation of voids at the interface due to mechanical stress caused by thermal expansion and material density changes during operation.
Additionally, due to variations in manufacturing processes the size of the small contact surface between electrodes and the phase change material will vary from cell to cell in an array. These variations may result in different programming characteristics including wide variations in the resulting resistance of the memory cells.
It is therefore desirable to provide memory cells having a small reset current while also addressing the issues of small contact surfaces between electrodes and phase change material as discussed above. Furthermore, it is desirable provide methods for manufacturing using reliable and repeatable techniques which produce small variations in the contact surfaces across an array of memory cells.